1. Field of the Invention
This invention relates to a semiconductor integrated circuit, and more specifically, to a semiconductor integrated circuit being capable of detecting timing error.
2. Background Art
As integration degree of semiconductor integrated circuits is enhanced and sizes of semiconductor elements composing the integrated circuits become small, production variation of the elements becomes large. As the variation becomes large, a circuit block whose operation is slow comes to exist in certain probability, and there is a problem that timing error is caused by too late operation of the circuit for the clock frequency. If the clock frequency is reduced for avoiding this, it becomes difficult to satisfy the required operation speed. Moreover, as the integrated degree becomes high, it becomes difficult to wire the clock with equal delay to a plurality of circuits on the chip, and noise becomes easy to mix in the power voltage. As a result, circuits causing timing error with a little variation are increased and there is a problem of yield lowering.
Conventionally, as a technique for avoiding timing error and soft error, such a method as described as US-A 2004/0199821 is known in a flipflop circuit holding data according to the clock signal. In this method, another latch circuit is provided in parallel to the flipflop on the pipeline and is used by a slightly delayed clock than the system clock to compare data contents held by both of the circuits, and if the data contents are different, it is determined that there is error and the data is calibrated.
However, in this method, one more latch circuit is required, and also, a comparison circuit for comparing data and a calibration circuit for calibrating data, and therefore, the scale of the circuits becomes large.